Associated with the rapid progress of semiconductor circuit integration techniques and the development of a higher integration of semiconductor elements, the technological revolution for semiconductor memory devices has been attempting to attain a larger capacity and further miniaturization. Particularly for flash memory devices, so-called chip shrinkage for decreasing chip size by means of an ultra-fine process techniques has been in progress. In particular, these ultra-fine process techniques have permitted decreasing the area of a arrays of memory cells each of which may store a respective bit.
Despite progress that has been made in decreasing the area of memory cell arrays, there remains a problem with decreasing the area of a column decoder connected to memory cell arrays for controlling data input to and output from the array.
In the flash memory depicted in FIG. 1, when an erase operation is being carried out to erase data in memory cells, the voltage of a control gate 101 of a selected memory cell is decreased to zero volts, and an erase voltage of approximately twenty volts is then usually applied to the entirety of a well 102 in which a memory cell array is placed. This causes any electrons accumulated in the floating gate of the selected memory cell to discharge to the well by virtue of a tunnel effect. While such an erase operation is being carried out, gates of transistors 104, 105, 106 and 107 sharing the well are maintained at the same potential. Therefore, a high voltage transistor need not be used for the transistors 104, 105, 106 and 107. This in turn makes it possible to design the cell array unit with a smaller pitch pattern and to have the thickness of a thin film.
On the other hand, when the high erase voltage is applied to the well, a similar voltage is coupled to a digit line (often referred to as a bit line) that is used to couple the memory cell to sensing circuitry, such as sense amplifiers. Therefore, a high voltage transistor, which is typically part of a column decoder, is typically used to selectively couple a bit line with a periphery circuit, such as a sense amplifier, to isolate the peripheral circuit from this difference of potentials. A high voltage transistor has a large film thickness and large gate length, resulting in a large size, and therefore it is very difficult to reduce the size of the column decoder beyond a certain area.
Furthermore, associated with the progress of chip shrinkage aiming at larger capacities of flash memory, there is a trend for the pitch pattern of bit lines to be ever narrower. While bit line intervals between the column decoder and cell array unit need to be equalized, there is a process difficulty in employing lithography in the semiconductor production process because the column decoder transistor in the column decoder is large, as described above.
A short-circuiting in such a column decoder is a large factor causing pitch failures in the conventional flash memory production devices. This problem has been solved to some extent, but some problems remain. For example, as shown in FIG. 1, a source line is fabricated in the well 102 as indicated by the arrow in the drawing. The control gate 101 of the selected memory cell is set to zero volts, that is, the row lines (often referred to as word lines) in a block of the memory array selected for erase are set to zero volts, and an erase voltage, such as 20 volts, is applied to the well 102. This event causes a control gate 103 of an unselected memory cell to be in a floating state. As a result, the voltage at each gate of a row select transistor 104, a drain select transistor 105, a first column decoder transistor 106 and second column decoder transistor 107 increases to twenty volts due to a coupling phenomenon with the well 102. This is followed by grounding the well 102 to decrease the erase voltage as shown in the lower row of FIG. 1.
In the step of decreasing the erase voltage, a breakdown phenomenon can occur in the p-n junction. The first column decoder transistor 106 and the second column decoder transistor 107 are in an off state to protect the periphery, which causes the p-n junction part on the well to be reversely biased because the electrons in the bit line are not discharged by way of the bit line. At the time of the occurrence of the breakdown phenomenon, a reverse voltage is generated to the respective gates of the source select transistor 104, drain select transistor 105, first column decoder transistor 106 and second column decoder transistor 107, which are put in the floating state, thus resulting in applying a high voltage (e.g., a reverse voltage) stress. A breakdown of the p-n junction part of each transistor on the well accompanies the reverse voltage, thereby decreasing the voltage of the bit line. Considering that the flash memory is actually used in repetitions of data writings and erasures, a reduction of voltage through breakdowns causes a very high possibility of damage to the flash memory device.